Below, the instruction set for the PowerPC architecture is given. A lot of instructions were intentionally left out:

  • Instructions for 64-bit Implementations Only
  • Floating Point Instructions
  • Supervisor-Level Instructions
  • I/O-specific Instructions
  • Instructions for Multiprocessor Support
  • Trap / System Call Instructions

This leaves 107 instructions: the core PowerPC Instruction Set.

When following the links below, you will be taken to a page describing a (family of) instructions. Note that these descriptions are taken from the 64-bit version of the instruction set; bit numbering are different for some instructions on 32-bit implementations. The lab course software uses a 32-bit PowerPC emulator.

The mnemonics column shows all valid forms of an instruction; it also shows simplified mnemonics in italics.

InstructionMnemonicsDescription
add add / add. / addo / addo. Add
addc addc / addc. / addco /addco. Add Carrying
adde adde / adde. / addeo /addeo. Add Extended
addi addi / li / la / subi Add Immediate
addic addic / subic Add Immediate Carrying
addic. addic. / subic. Add Immediate Carrying and Record
addis addis / lis / subis Add Immediate Shifted
addme addme / addme. / addmeo / addmeo. Add to Minus One Extended
addze addze / addze. / addzeo / addzeo. Add to Zero Extended
and and / and. AND
andc andc / andc. AND with Complement
andi. andi. AND Immediate
andis. andis. AND Immediate Shifted
b b / ba / bl / bla Branch
bc bc /bca / bcl bcla Branch Conditional
bcctr bcctr / bcctrl Branch Conditional to Count Register
bclr bclr / bclrl Branch Conditional to Link Register
cmp cmp / cmpw Compare
cmpi cmpi / cmpwi Compare Immediate
cmpl cmpl / cmplw Compare Logical
cmpli cmpli / cmplwi Compare Logical Immediate
cntlzw cntlzw / cntlzw. Count Leading Zeros Word
crand crand Condition Register AND
crandc crandc Condition Register AND with Complement
creqv creqv / crset Condition Register Equivalent
crnand crnand Condition Register NAND
crnor crnor / crnot Condition Register NOR
cror cror / crmove Condition Register OR
crorc crorc Condition Register OR with Complement
crxor crxor / crclr Condition Register XOR
divw divw / divw. / divwo / divwo. Divide Word
divwu divwu / divwu. / divwuo / divwuo. Divide Word Unsigned
eqv eqv / eqv. Equivalent
extsb extsb / extsb. Extend Sign Byte
extsh extsh / extsh. Extend Sign Half Word
lbz lbz Load Byte and Zero
lbzu lbzu Load Byte and Zero with Update
lbzux lbzux Load Byte and Zero with Update Indexed
lbzx lbzx Load Byte and Zero Indexed
lha lha Load Half Word Algebraic
lhau lhau Load Half Word Algebraic with Update
lhaux lhaux Load Half Word Algebraic with Update Indexed
lhax lhax Load Half Word Algebraic Indexed
lhbrx lhbrx Load Half Word Byte-Reverse Indexed
lhz lhz Load Half Word and Zero
lhzu lhzu Load Half Word and Zero with Update
lhzux lhzux Load Half Word and Zero with Update Indexed
lhzx lhzx Load Half Word and Zero Indexed
lmw lmw Load Multiple Word
lswi lswi Load String Word Immediate
lswx lswx Load String Word Indexed
lwbrx lwbrx Load Word Byte-Reversed Indexed
lwz lwz Load Word and Zero
lwzu lwzu Load Word and Zero with Update
lwzux lwzux Load Word and Zero with Update Indexed
lwzx lwzx Load Word and Zero Indexed
mcrf mcrf Move Condition Regisiter Field
mcrxr mcrxr Move to Condition Register from XER
mfcr mfcr Move from Condition Register
mfspr mfspr / mfxer / mflr / mfctr Move from Special-Purpose Register
mftb mftb Move from Time Base
mtcrf mtcrf Move to Condition Register Fields
mtspr mtspr / mtxer / mtlr / mtctr Move to Special-Purpose Register
mulhw mulhw / mulhw. Multiply High Word
mulhwu mulhwu / mulhwu. Multiply High Word Unsigned
mulli mulli Multiply Low Immediate
mullw mullw / mullw. / mullwo / mullwo. Multiply Low Word
nand nand / nand. NAND
neg neg / neg. / nego / nego. Negate
nor nor /nor. NOR
or or / or. OR
orc orc / orc. OR with Complement
ori ori OR Immediate
oris oris OR Immediate Shifted
rlwimi rlwimi / rlwimi. / inslwi / insrwi Rotate Left Word Immediate then Mask Insert
rlwinm rlwinm / rlwinm. / extlwi / extrwi
rotlwi / rotrwi / slwi / srwi
clrlwi / clrrwi / clrlslwi
Rotate Left Word Immediate then AND with Mask
rlwnm rlwnm / rlwnm. / rotlw Rotate Left Word then AND with Mask
slw slw / slw. Shift Left Word
sraw sraw /sraw. Shift Right Algebraic Word
srawi srawi / srawi. Shift Right Algebraic Word Immediate
srw srw / srw. Shift Right Word
stb stb Store Byte
stbu stbu Store Byte with Update
stbux stbux Store Byte with Update Indexed
stbx stbx Store Byte Indexed
sth sth Store Half Word
sthbrx sthbrx Store Half Word Byte-Reverse Indexed
sthu sthu Store Half Word with Update
sthux sthux Store Half Word with Update Indexed
sthx sthx Store Half Word Indexed
stmw stmw Store Multiple Word
stswi stswi Store String Word Immediate
stswx stswx Store String Word Indexed
stw stw Store Word
stwbrx stwbrx Store Word Byte-Reverse Indexed
stwu stwu Store Word with Update
stwux stwux Store Word with Update Indexed
stwx stwx Store Word Indexed
subf subf / subf. / subfo / subfo. / sub Subtract From
subfc subfc / subfc. / subfco / subfco. / subc Subtract from Carrying
subfe subfe / subfe. / subfeo. / subfeo. Subtrect from Extended
subfic subfic Subtract from Immediate Carrying
subfme subfme / subfme. / subfmeo / subfmeo. Subtract from Minus One Extended
subfze subfze / subfze. / subfzeo / subfzeo. Subtract from Zero Extended
xor xor / xor. XOR
xori xori XOR Immediate
xoris xoris XOR Immediate Shifted

출 처 : http://pds.twi.tudelft.nl/vakken/in1200/labcourse/instruction-set/

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