OPERATING MODE
REGISTER (OMR, R, ADDRESS = 0XE000_0004)
< hkdkc100\config.mk 파일에서 >
ifndef TEXT_BASE
//TEXT_BASE = 0xc7e00000
TEXT_BASE = 0x27e00000
endif
< hkdkc100.h(45) 파일에서>
#define CONFIG_S5PC100_EVT2
#define BOOT_ONENAND 0x1
#define BOOT_NAND 0x2
#define BOOT_MMCSD 0x3
#undef CONFIG_ENABLE_MMU
#define CONFIG_MEMORY_UPPER_CODE
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
< cpu/s5pc1xx/start.s 파일에서 >
///////////////////////////////////////////////////////////////
/* Read booting information *
ldr r0, =PRO_ID_BASE ; PRO_ID_BASE = 0XE000_000
ldr r1, [r0,#OMR_OFFSET] ; OMR_OFFSET = 0x04
bic r2, r1, #0xfffffff9
cmp r2, #0x0
moveq r3, #BOOT_NAND
cmp r2, #0x2
moveq r3, #BOOT_ONENAND
cmp r2, #0x4
moveq r3, #BOOT_MMCSD
ldr r0, =INF_REG_BASE
str r3, [r0, #INF_REG3_OFFSET]
/*
* Go setup Memory and board specific bits prior to relocation.
*/
bl lowlevel_init /* go setup pll,mux,memory */
/* when we already run in ram, we don't need to relocate U-Boot.
* and actually, memory controller must be configured before U-Boot
* is running in ram.
*/
ldr r0, =0xff000fff
bic r1, pc, r0 /* r0 <- current base addr of code */
ldr r2, _TEXT_BASE /* r1 <- original base addr in ram */
bic r2, r2, r0 /* r0 <- current base addr of code */
cmp r1, r2 /* compare r0, r1 */
beq after_copy /* r0 == r1 then skip flash copy */
ldr r0, =INF_REG_BASE
ldr r1, [r0, #INF_REG3_OFFSET]
cmp r1, #BOOT_NAND /* 0x0 => boot device is nand */
beq nand_boot
cmp r1, #BOOT_ONENAND /* 0x1 => boot device is onenand */
beq onenand_boot
cmp r1, #BOOT_MMCSD
beq mmcsd_boot
출처 : http://blog.naver.com/serimo/50091184494
Field Bit
Description
Reset Value
Reserved [31:18] Read as zero 0x0
Reserved [17] Read as one 1
Reserved [16] Read as one 1
Reserved [15:14] Read as zero 0x0
NFMOD [13:8] The value of the
XNFMOD[5:0] pad Pin value
Reserved [7:5] Read as zero 0x0
OM [4:0] The
value of
the XOM[4:0] pad Pin value
OM[4]:
0 = normal mode, 1 = test mode
OM[3]:
0 = 1st boot loader in iROM , 1 =
reserved
OM[2:1] :
00 = 2nd boot
loader in NAND
flash
01 = 2nd boot
loader in OneNAND
10 = 2nd boot loader
in MMC
11 = Reserved
OM[0] : APLL/MPLL input selection
0 = XXTI
1 = XusbXTI
< hkdkc100\config.mk 파일에서 >
ifndef TEXT_BASE
//TEXT_BASE = 0xc7e00000
TEXT_BASE = 0x27e00000
endif
< hkdkc100.h(45) 파일에서>
#define CONFIG_S5PC100_EVT2
#define BOOT_ONENAND 0x1
#define BOOT_NAND 0x2
#define BOOT_MMCSD 0x3
#undef CONFIG_ENABLE_MMU
#define CONFIG_MEMORY_UPPER_CODE
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
< cpu/s5pc1xx/start.s 파일에서 >
///////////////////////////////////////////////////////////////
/* Read booting information *
ldr r0, =PRO_ID_BASE ; PRO_ID_BASE = 0XE000_000
ldr r1, [r0,#OMR_OFFSET] ; OMR_OFFSET = 0x04
bic r2, r1, #0xfffffff9
cmp r2, #0x0
moveq r3, #BOOT_NAND
cmp r2, #0x2
moveq r3, #BOOT_ONENAND
cmp r2, #0x4
moveq r3, #BOOT_MMCSD
ldr r0, =INF_REG_BASE
str r3, [r0, #INF_REG3_OFFSET]
/*
* Go setup Memory and board specific bits prior to relocation.
*/
bl lowlevel_init /* go setup pll,mux,memory */
/* when we already run in ram, we don't need to relocate U-Boot.
* and actually, memory controller must be configured before U-Boot
* is running in ram.
*/
ldr r0, =0xff000fff
bic r1, pc, r0 /* r0 <- current base addr of code */
ldr r2, _TEXT_BASE /* r1 <- original base addr in ram */
bic r2, r2, r0 /* r0 <- current base addr of code */
cmp r1, r2 /* compare r0, r1 */
beq after_copy /* r0 == r1 then skip flash copy */
ldr r0, =INF_REG_BASE
ldr r1, [r0, #INF_REG3_OFFSET]
cmp r1, #BOOT_NAND /* 0x0 => boot device is nand */
beq nand_boot
cmp r1, #BOOT_ONENAND /* 0x1 => boot device is onenand */
beq onenand_boot
cmp r1, #BOOT_MMCSD
beq mmcsd_boot
출처 : http://blog.naver.com/serimo/50091184494